Frequency dividers may be used to generate lower-frequency signals from higher-frequency signals. Some frequency dividers may generate an output clock having a frequency that is equal to 1/N times the frequency of an input clock, where N is an integer greater than 1. Some frequency dividers may propagate an input signal through a series of flip-flops that are clocked on rising edges of a clock signal, for example, so that each of the flip-flops generates an output signal that is an incrementally delayed version of the input signal. Edge transitions of the flip-flop output signals may be used to divide the period of the input clock by the value of N. For example, if the delay between the flip-flop output signals is equal to the period of the input signal, then the rising edge of the output signal generated by the Nth flip-flop may be used to generate the divide-by-N output signal.
Other frequency dividers may generate an output signal having a frequency that is 1/(N+0.5) times the frequency of an input signal, where N+0.5 is a non-integer greater than one. These frequency dividers, which may be referred to as fractional frequency dividers, may also propagate an input signal through a series of flip-flops that are clocked by a clock signal, for example, so that each of the flip-flops generates an output signal that is an incrementally delayed version of the input signal. Unlike divide-by-N frequency dividers, fractional frequency dividers typically clock the series of flip-flops using both the rising edges and the falling edges of the input clock, for example, to identify the half-cycle of the input clock. For example, if first edge transitions of a given flip-flop output signal resulting from rising edges of the input clock align with edge transitions of the input signal, then second edge transitions of the given flip-flop output signal resulting from falling edges of the input clock may be aligned with half-periods of the input signal.
If the duty cycle of the input clock is not equal to 50%, then the edge transitions of the flip-flop output signals may not be equally spaced apart, which may degrade accuracy (such as because one or more of the edge transitions may not align with the half-period of the input signal. In addition, if both the rising and falling edges of the input clock are used to generate the incrementally delayed flip-flop output signals, then the critical timing path of the fractional frequency divider may be one half of the period of the input clock (rather than a full period of the input clock), which in turn may reduce processing time of the fractional frequency divider by as much as one-half (as compared to a divide-by-N frequency divider).